A digital storage subsystem, such as a solid-state "disk drive" includes a storage controller and an array composed of dynamic random access memory (DRAM) devices. The controller is physically separated from the array so that individual DRAM-based array modules may use a common storage control function. In that way, the storage capacity of the subsystem may easily be increased or decreased as required.
The storage subsystem provides high transfer rates, i.e. block-mode transfers of data to and from a main memory, and fast access. A block-mode transfer involves the transmission of a plurality of data words to or from a predetermined number of addressed locations in the DRAM array. Typically, a starting binary address associated with the block of data is provided to the controller. The controller thereafter generates a predetermined number of sequential addresses, typically with the use of counters. The addresses are then transferred as signals to the appropriate memory array modules.
It is important that the transferred address signals be error-free to ensure reliable storage and retrieval of data to and from the DRAM locations. Accordingly, error detection codes are used to detect errors in the transfer of the address signals. A common address error detection code is the parity bit, which is an extra bit included with the address bits to make the total number of ones either odd or even. However, the use of such a code in connection with a binary counter requires extensive manipulation to determine parity since different numbers of bit positions are altered for successive addresses.
Gray code counters have been used in conjunction with parity code systems to provide cost-effective address error detection. The advantage of Gray code over straight binary numbers is that the Gray code changes by only one bit as it sequences from one number to the next. Gray code counters thus remove multiple-bit ambiguities during the change from one state of a counter to the next because only one bit changes during the state transition. Accordingly, easily-derived, one-bit parity checks can be used. Nevertheless, the mere detection of an address error is insufficient to ensure the integrity of data stored in the DRAM array. That is, the occurrence of an address error during a write operation may still result in data being stored at an erroneous address and corrupting the previously stored data at that location.